Curriculum
Curriculum in detail
Full-cycle map, stages in each field, who can join, facilities
Full-cycle map: where each course sits among the eight fab processes
DESIGN fields ① ② ③
① DevicesDevice designTCAD device & process simulation (Silvaco) — transistor structure · doping
② CircuitsCircuit designSimulation & layout courses — industrial EDA
③ SystemsSystem designVerilog · FPGA · RISC-V · SoC
FRONT-END six fab steps · field ①
①Wafer fabricationHands-on at partner facilities · visits
①OxidationIntro practice on campus + advanced at partner fabs
①LithographyIntro practice on campus + advanced at partner fabs
①EtchIntro practice on campus + advanced at partner fabs
①Deposition · implantIntro practice on campus + advanced at partner fabs
①MetallizationHands-on at partner facilities — linked to layout
BACK-END two steps · field ④
④EDS testReal chip measurement on a probe station (from 2027)
④PackagingHands-on wire bonding — part of the packaging flow (from 2027)
VERIFY · BUILD ③ ④
④Test & measurementMeasurement course — device · circuit · chip
③ ④Module buildA board around your own chip · FPGA-linked system
Hands-on on campusIntro on campus + advanced at partner fabsHands-on at partner facilities (KANC, NNFC and others)
Chips designed here are fabricated at an external foundry through an MPW run. Measuring the returned chip and building a module with it completes the cycle.
Stages in each field
| Field | Theory basics (online) | Foundation labs | Practical I | Practical II & lectures |
|---|---|---|---|---|
| ① Device design & process | Semiconductor physics · devices | Device characteristics · TCAD basics · process intro | Device design I · partial fab practice | Advanced devices & processes (partner fabs · lectures) |
| ② Circuit design & fabrication | Circuit theory · electronics · RF basics | DC characteristics · S-parameters · EDA basics | Amplifiers · Op-amp to LDO · LNA · VCO · layout | ADC · DC-DC · transceivers · tape-out |
| ③ System design | Digital logic · computer architecture | Verilog · tool basics | FPGA · RISC-V | NPU · AI accelerators · SoC |
| ④ Test & measurement | Instrument basics · test overview | Oscilloscope · DC supply basics | Device I-V · circuit performance · module measurement | Chip probing · wire-bond packaging (from 2027) · module build |
The seven theory courses will be released online in 2027 through the JOY shared-university platform and other channels, open to anyone regardless of major or school. Lab courses follow the theory basics.
Who can join
Who can join
- UGJNU electronics studentsAfter Circuit Theory and Electronic Circuits (from the 2nd-year winter break)
- LOCALOther JNU departments & schools in JejuTake the online theory basics (from 2027, JOY platform) and then join the labs
- GRADGraduate studentsDesign and measurement skills for research
- INTLInternational students, researchers and engineersWelcome from anywhere in the world — English subtitles, materials and interpreters
- PROWorking engineersShort courses such as FPGA and RF/MMIC
- HSHigh-school studentsCareer talks and hands-on camps during school breaks
Facilities
Facilities
Teaching labs · server room
Engineering Building 3, Jeju National University. Separate design and measurement labs; a GPU server runs simulation and design tools.
Industrial EDA tools · instruments
Cadence, Siemens, Synopsys and Silvaco design tools, and instruments such as oscilloscopes, set up as they would be in industry.
Workation space
An open space at the Jeju Knowledge Industry Center for working-engineer courses, lectures and company collaboration.